In response to a demand for miniaturization and increased performance of power source instruments in the field of power electronics in recent years, efforts are being centered on increasing breakdown voltage and increasing current in power semiconductor devices, as well as improving performance with regard to reducing loss, increasing damage tolerance, and increasing speed. Then, a vertical trench MOS (metal/oxide/semiconductor) gate power device is used as a power semiconductor device with which increased current and reduced loss are possible.
An MOS power device, in particular an IGBT, is driven by an MOS gate, and two kinds of structure are widely known—a planar structure wherein a plate-like gate electrode is provided across an insulating film on a semiconductor substrate, and a trench structure wherein a gate electrode is embedded across an insulating film inside a semiconductor substrate. Among recent vertical devices, a structure wherein a gate electrode is embedded inside a trench—a so-called trench gate type—is attracting attention. With a trench gate type vertical device, it is structurally easy to obtain a low on-resistance characteristic.
A typical structure of this kind of trench gate type IGBT is a structure wherein a p-type base region and an n-type drift region with a concentration lower than that of the base region appear alternately in the longitudinal direction of a gate trench in which a gate electrode is embedded across an insulating film (for example, refer to Patent Document 1 below). The vertical trench gate type IGBT is commonly known as an IGBT with which low on-resistance and high breakdown voltage can be simultaneously realized. In the following description, a device means a vertical type unless particularly stated otherwise.
A description will be given, while referring to FIGS. 33 to 35, of a structure of the trench gate type IGBT and operations thereof. FIG. 33 is a plan view schematically showing main portions of a heretofore known semiconductor device. Also, FIG. 34 is an explanatory diagram schematically showing main portions of the heretofore known semiconductor device. FIG. 35 is a sectional view schematically showing main portions of the heretofore known semiconductor device. FIG. 33(a) shows a planar structure of the heretofore known trench gate type IGBT shown in FIG. 34(a). FIG. 34(a) is a perspective view showing the structure of the heretofore known trench gate type IGBT. Then, FIGS. 33(b), 34(b), 35(a), and 35(b) show current paths of the heretofore known trench gate type IGBT shown in FIG. 34(b).
As shown in FIG. 34(a), a p-type base region 12 is selectively provided on one main surface (hereafter referred to as the front surface) of a semiconductor substrate, which is an n-type drift region 11. The p-type base region 12 and n-type drift region 11 are alternately exposed on the front surface of the semiconductor substrate. Also, a large number of gate trenches 13 are provided intersecting the p-type base region 12 on the front surface of the semiconductor substrate. The gate trench 13 is formed penetrating the p-base region 12 to a depth reaching the n-type drift region 11. A gate oxide film 14 is formed on the inner wall of the gate trench 13, and furthermore, a gate electrode 15 formed of poly-crystalline silicon (Si), or the like, is formed buried in the interior of the gate oxide film 14.
Then, a p-type contact region 17 is disposed between neighboring gate trenches 13, distanced from the gate trenches 13, in a surface layer of the p-type base region 12. Also, an n-type emitter region 16 is provided, adjacent to each of the p-type contact region 17 and gate trench 13, in the surface layer of the p-type base region 12. An n-type field stop region 50 and a p-type collector region 51 are provided on the other main surface (hereafter referred to as the rear surface) of the semiconductor substrate. The n-type field stop region 50 is provided between the n-type drift region 11 and p-type collector region 51. A collector electrode 22 is in contact with the p-type collector region 51.
FIG. 34(b) is a sectional view along a cross-section A of the trench gate type IGBT shown in FIG. 34(a). FIG. 34(b) schematically shows current paths in the cross-section A. The cross-section A is a cross-section that intersects the lateral direction of the gate trench 13. As shown in FIG. 34(b), an insulating film 18 is provided on the front surface (hereafter referred to as the top surface) of the gate electrode 15. An emitter electrode 19 formed of, for example, aluminum (Al), or the like, is formed over the whole of an active region on the front surface of the semiconductor substrate. The emitter electrode 19 is in ohmic contact with the n-type emitter region 16 and p-type contact region 17. Also, the emitter electrode 19 and gate electrode 15 are dielectrically isolated by the insulating film 18.
In the heretofore known trench gate type IGBT, an n-type inversion layer is formed in a region of the p-type base region 12 along the trench by applying a voltage of a predetermined threshold value or higher to the gate electrode 15, and a current path passing through the n-type inversion layer is formed, as shown in FIG. 34(b). Because of this, there is an on-condition between the emitter and collector of the trench gate type IGBT. Meanwhile, by reducing the voltage of the gate electrode 15 to the threshold value or lower, the n-type inversion layer of the p-type base region 12 disappears, and there is an off-condition between the emitter and collector of the trench gate type IGBT.
FIG. 35(a) is a sectional view along a cross-section B of the trench gate type IGBT shown in FIG. 34(a). Also, FIG. 35(b) is a sectional view along a cross-section C of the trench gate type IGBT shown in FIG. 34(a). FIGS. 35(a) and 35(b) schematically show current paths in the cross-sections B and C respectively. The cross-section B is a cross-section along a side wall in the longitudinal direction of the gate trench 13. The cross-section C is a cross-section that intersects the p-type base region 12 between neighboring gate trenches 13 parallel to the gate trench longitudinal direction.
As shown in FIGS. 35(a) and 35(b), according to the heretofore known trench gate type IGBT, trench type (FIG. 35(a)) and planar type (FIG. 35(b)) current paths are formed in the longitudinal direction of the gate trench 13. Because of this, the area of the current paths increases dramatically in comparison with a heretofore known planar type or trench type vertical IGBT. Furthermore, an accumulation of minority carriers occurs in a region in which the n-type semiconductor substrate is exposed between gate trenches 13 on the front surface side of the semiconductor substrate, and there arises an advantage in that it is possible to reduce on-resistance.
A planar structure of one portion of the heretofore known trench gate type IGBT shown in FIG. 34(a) is shown in configuration units in FIG. 33(a). As shown in FIG. 33(a), the p-type base region 12 is disposed in a mesa region 47 between neighboring gate trenches 13 so as to be in contact with each gate trench 13. The n-type emitter region 16 forming an H-shape is provided in the p-type base region 12 so as to be in contact with each of the neighboring gate trenches 13. Also, the p-type contact region 17 is disposed in an approximate central portion of the p-type base region 12 in order to prevent a latch-up of a parasitic thyristor portion. Herein, the n-type emitter region 16 is formed so as to straddle the top surface of the p-type contact region 17. That is, an edge portion of the n-type emitter region 16 does not terminate inside the p-type contact region 17.
In this type of heretofore known trench gate type IGBT, a hole current flows in the following way. FIG. 33(b) is a plan view wherein a hole (also called positive hole) current flow 40 when a current is flowing through the IGBT with the gate of the IGBT in an on-condition, and a region 41 in which hole currents collect, are schematically shown in the plan view of the heretofore known IGBT shown in FIG. 33(a). When the gate of the IGBT is in an on-condition, as heretofore described, electrons are implanted from the MOS gate into the n-type drift region 11. The electrons implanted into the n-type drift region 11 reach a p-type collector region of the IGBT omitted from the drawing. Then, holes are implanted from the p-type collector region into the n-type drift region 11, and flow toward the p-type base region 12 of the front surface of the IGBT following an electrostatic potential distribution.
At this time, the holes are attracted toward the electrons by coulomb force, and flow toward an electron inversion layer (also called a channel, or inversion layer channel) formed in a region of the p-type base region 12 in contact with a side wall of the gate trench 13. That is, as indicated by arrows in FIG. 33(b), the hole current flows 40 mainly concentrate in the region of the p-type base region 12 in contact with a side wall of the gate trench 13. Because of this, the hole current is such that there are sufficiently few components of the hole current that pass from the n-type drift region 11 through the p-type contact region 17 after passing directly through the p-type base region 12.
Also, as another example of the trench gate type IGBT, there is disclosed an IGBT wherein the disposition of a contact aperture portion is innovated in an IGBT with a structure similar to that of Patent Document 1 below (for example, refer to Patent Document 2 below). A description will be given, referring to FIGS. 36 to 38, of the IGBT wherein the disposition of the contact aperture portion is innovated. FIGS. 36 to 38 are plan views schematically showing main portions of another example of the heretofore known semiconductor device. FIG. 37 shows the hole current flow and the region 41 in which hole currents collect in the heretofore known trench gate type IGBT shown in FIG. 36.
FIG. 38 shows a planar structure of a minimum unit in a surface portion in the heretofore known trench gate type IGBT shown in FIG. 36. As shown in FIG. 38, a contact aperture 46 longer in the longitudinal direction (vertically in the plane of the drawing) of the gate trench 13 than the n-type emitter region 16 is formed in order to improve the latch-up capability of the IGBT. Also, as shown in FIGS. 36 and 37, plural p-type base regions 12 formed between two gate trenches 13 are disposed in like a check pattern.
Furthermore, as another example of the trench gate type IGBT, there is disclosed an IGBT wherein the disposition of the n-type emitter region 16 is innovated (for example, refer to Patent Document 3 below). A description will be given, referring to FIG. 39, of the IGBT wherein the disposition of the n-type emitter region 16 is innovated. FIG. 39 is a perspective view schematically showing main portions of another example of the heretofore known semiconductor device. As shown in FIG. 39, the n-type emitter region 16 in contact with only one gate trench 13 in a region between two neighboring gate trenches 13 is disposed so as to be in contact with the two gate trenches 13 alternately. By the n-type emitter region 16 being disposed in this way, the latch-up capability is improved.
Also, as another example of the trench gate type IGBT, there is disclosed a structure wherein a contact trench with an object of contact with the emitter electrode is formed in a mesa region between two gate trenches, and a desired region (n-type emitter region, p-type contact region, contact portion, or the like) is formed in accordance with the form of the contact trench (for example, refer to Patent Document 4 below). By this kind of contact trench being formed, the width of a contact region formed between two gate trenches is made one region smaller, enabling a miniaturization of a surface pattern.